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Application Note 9862
current draw exceeds 1A). For most, if not all cases, neither
W1 nor W2 need be shorted.
Design Envelope
Although different computer systems might have different
requirements, the HIP6500BEVAL1 and HIP6502BEVAL1
boards were designed to meet the maximum output loading
described in Tables 1 and 2. Note the fact that the addition of
all the sleep state output currents exceeds the typical ATX
power supply 5VSB output capability (725mA). Real-life
sleep state current requirement on each of the outputs could
be lower, and their maximums should rarely all occur
simultaneously. Output tolerances and current ratings (with
the exception of the 2.5V CLK , 3.3V SB , and 2.5/3.3V MEM
when operating on internal pass transistors) can be adjusted
by properly selecting the components external to the
HIP6500B/02B.
TABLE 1. HIP6500BEVAL1 MAXIMUM OUTPUT LOADING
HIP6500B/02BEVAL1 Performance
Figures 2 through 6 depict the evaluation board’s
performance during a few typical operational situations. To
simulate minimum loading conditions, unless otherwise
specified, the outputs were loaded with 65 Ω resistive loads.
Sleep-State Start-Up
Figure 2 shows a typical HIP6500BEVAL1 start-up into S3
sleep state while all outputs are enabled (EN3VDL = 0,
EN5VDL = 1). As 5VSB is applied to the board, SW1 and
SW3 are off, while SW2 is on. At time T0 the input supply
exceeds the power-on-reset (POR) threshold. Three
milliseconds afterwards, at time T1, the soft-start clamp is
removed and the 3.3V SB output starts to ramp up toward its
target value, which it reaches at time T2. As its ramping
ends shortly after bringing up this first output, the soft-start
voltage is quickly brought down and prepared for a second
soft-start designed to bring up the remainder of the
OUTPUT
VOLTAGE
2.5V CLK
2.5/3.3V MEM
ACTIVE STATES
I OUT dI OUT /dt
500mA 0.1A/ μ s
4A 1A/ μ s
SLEEP STATES TOL.
I OUT dI OUT /dt DYNAMIC)
0 0 5% / 5%
250mA 1A/ μ s 5% / 9%
(Note) (Note)
(STATIC/
controlled voltages that are supported in this configuration
and state. This second ramp-up begins at time T3 and ends
at time T4. The 5V DUAL output has a slightly different ramp-
up than the remainder of the output voltages. The 5V DUAL
output is not actively regulated, as is the case with the
2.5V MEM and 3.3V DUAL outputs in S3, but rather switched
on through a P-MOS or PNP switch. An error amplifier is
3.3V SB
3.3V DUAL
5V DUAL
150mA
3A
2.5A
0.1A/ μ s
0.2A/ μ s
0.1A/ μ s
50mA
600mA
200mA
0.1A/ μ s
0.2A/ μ s
0.1A/ μ s
5% / 5%
9% / 9%
9% / 9%
thus provided for the 5V DUAL output just for the purpose of
providing a smooth, controlled output voltage rise. This error
amplifier uses a different, soft-start derived, ramp signal to
achieve the controlled rise of the output.
NOTE: S3 State Only.
TABLE 2. HIP6502BEVAL1 MAXIMUM OUTPUT LOADING
OUTPUT
ACTIVE STATES
SLEEP STATES
TOL.
(STATIC/
5VSB
VOLTAGE
2.5V CLK
I OUT
500mA
dI OUT /dt
0.1A/ μ s
I OUT
0
dI OUT /dt
0
DYNAMIC)
5% / 5%
5V DUAL
3.3V SB
2.5V MEM
3.3V MEM
3.3V DUAL /
3.3V SB
5V DUAL
4A
4A
3A
2.5A
1A/ μ s
1A/ μ s
0.2A/ μ s
0.1A/ μ s
250mA
(Note)
250mA
(Note)
600mA
200mA
1A/ μ s
(Note)
1A/ μ s
(Note)
0.2A/ μ s
0.1A/ μ s
5% / 9%
5% / 9%
9% / 9%
9% / 9%
GND>
3.3V DUAL
10ms/DIV
2.5V MEM
2.5V CLK
NOTE: S3 State Only.
T0 T1
T2 T3
T4
FIGURE 2. HIP6500BEVAL1 START-UP IN SLEEP STATE
The maximum current supported on the 2.5V MEM output
(systems employing RDRAM memory) is as high as 7-8A.
From a thermal performance perspective, do not operate the
evaluation board for extended periods of time at output
current levels exceeding the design envelope, as detailed in
Tables 1 and 2.
3
(S3) WITH ALL OUTPUTS ENABLED
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